With the miniaturization of electronic devices and increase of circuit density in semiconductor industry, technology of chip size package (CSP) is now under great development, of which the package size is similar to the semiconductor chip encased therein. The ratio of a typical CSP to the edge dimension is no larger than 120% as defined by Joint Electron Device Engineering Council (JEDEC). Compared with the conventional packaging technology, such as wire bonding, tape automatic bonding (TAB) and flip chip, CSP has following advantages: ultra-small package reaching the original size, full protection on the bare die, good electrical and heat performances, convenient for tests, easy to be welded, assembled and replaced. CSP is manufactured either in the form of individual chips diced from a wafer, or in a wafer form and then individual chip size packages are singulated from the wafer. The latter is referred to as a wafer level chip size package (WLCSP).
For WLCSP, generally a plurality of compatible pads formed in a peripheral arrayed type on semiconductor chips are redistributed through conventional redistribution processes involving a redistribution layer into a plurality of metal pads, sometimes called solder bumps, in an area array type. Since packaging and testing are performed at wafer level and then the wafer is diced, WLCSP has significant advantages as follows: Firstly, the process is optimized to perform packaging directly at wafer level, whereas, for prior art methods, the wafer has to be diced and classified before being packaged; secondly, packaging, marking and testing are all performed at wafer level; therefore the production cycle and cost are significantly reduced.
Shellcase Co. Israel developed its unique and advanced WLCSP technologies as ShellOP, ShellOC, and ShellUT to package image sensors, as disclosed in U.S. Pat. Nos. 6,646,289, 6,777,767 and 6,972,480. Unlike many packaging methods, the Shellcase process requires no lead frames or wire bonding. Briefly, ShellOP utilizes a glass/silicon/glass sandwiched structure to enable image-sensing capabilities through the actual packaging structure so as to protect the sensors from being contaminated by external environment. ShellOC adopts the same sandwich structure, but extra cavities are configured on a first glass by spinning photo-imageable epoxy on the glass to form a pattern with lithography technique, for accommodating the above imagers. Also, cavities enable the use of micro-lenses for enhancing image quality. ShellOC is thus a packaging solution to choice of image sensors with micro-lenses. In the ShellUT package, cavities are still kept but a second glass is removed so that the related package height is reduced.
FIG. 1 is a typical cross-section view of a packaged chip device by prior art ShellOC, wherein a first/top glass with cavity walls thereon covers compatible pads furnished silicon chip. An epoxy is used to bond a second/bottom glass to the chip on which a portion of compatible pads have been exposed before using photolithography and plasma etching techniques. After a barrier solder mask is coated on the second glass, notching is performed so that inverted leads, via sputtering deposition, connect electrically to the compatible pads in form of a so-called T-shape junction. The leads are coated with a protective solder mask thereon. The solder mask is a dielectric material that electrically isolates the leads from external contacts, and protects the lead surface against corrosion. Solder bumps are attached to the bottom end of leads, and are suitable for printed circuit board (PCB) mounting by known methods. Solder bumps may be formed by known methods like screen printing. FIG. 2 is a typical cross-section view of a packaged chip device by prior art ShellOP. FIG. 3 is a typical cross-section of a packaged chip device by prior art ShellUT.
MEMS is a kind of tiny mechanical device that is built onto semiconductor chips and is measured in micrometers. It makes use of silicon micromachining technology, LIGA (Lithograpie Galvanoformung Abformung) and precision mechanical engineering technology to fabricate microscopic mechanisms on the surface of a semiconductor wafer. MEMS has a wide range of applications, such as accelerometers, pressure sensors, actuators and many others. In any case above, MEMS devices are usually adapted to employ spatially active elements (gears, hinges, slides, etc) which must be typically free to move and therefore require a cavity surrounding.
Good packaging techniques are relatively more important for the successful performance of the components. The conventional packaging techniques for MEMS devices are ceramic package and metal package, both of them can provide a strong and hermetic enough component. However, both of them are ordinarily very expensive, for many conventionally produced MEMS components, the processes of packaging may take up about 70-85% from the total fabrication cost. Moreover, the packages in most cases are not small enough for handhold applications like cell phones. It is well-known that price and size are the two factors which are most sensitive in customer electronics that ought to be the biggest market of MEMS devices.
Although the Shellcase technique is quite suitable for optical and image sensors, e.g., charge-coupled devices (CCD) and/or CMOS imagers integrated on a silicon wafer, it is actually not fully satisfiable for MEMS devices.
First, in most cases, MEMS package has to provide inert gas filling in or high vacuum so as to protect the fragile movable parts, which requires high hermetic packaging, but the epoxy made cavity wall by conventional Shellcase technique is impossible to handle this. Secondly, many MEMS devices make use of inner gas as a medium. For example, a kind of MEMS accelerometer places sensors at certain position to detect the heat distribution of the inner gas so that it can monitor the movement of the gas and accordingly convert to the value of acceleration. In this case, the more gas filled in, the more sensitive this device would be. In order to get a better performance, it is necessary to make cavities on the cap substrate. But these cavities will make it difficult to form cavity wall, it is easy to understand that spin coating can only be performed on flat surface unless the uniformity of coating is out of concern. Thirdly, because of its complex structure, substrate wafer can not be thinned as much as in general IC wafer, with a typical thickness of about 400-500 um rather than 100 um. Under this circumstance, traditional RIE process can hardly ensure well enough groove shape and well enough uniformity.
Therefore, there is a need of wafer level chip size package for MEMS devices which would reduce both of the packaged size and cost. This package technique must provide a well controlled cavity within which micro-machined parts are free to move, allowing access to electrical contacts, and optimized for device performance.